As semiconductor devices have become more highly integrated, the size of the unit cells in the semiconductor devices has decreased. By way of example, the unit cells in state of the art dynamic random access memory (DRAM) devices now have widths of about 100 nm or less. To form such unit cells, semiconductor manufacturing tecliniques have been developed that may be used to form very small patterns, pads, contacts, and the like. One such technique is a self-alignment process that may be used to form extremely small contacts or pads.
Korean Laid-Open Patent Publication No. 2003-56321 discloses one conventional method of manufacturing a semiconductor device by employing such a self-alignment process. In this conventional self-alignment process, a gate structure is formed on a substrate that has an active region and a field region defined therein. The gate structure includes a gate oxide pattern, a gate electrode and a gate mask. A spacer is formed on a sidewall of the gate structure, and then a contact region is formed in the substrate adjacent to the gate structure. After an insulating interlayer is formed on the substrate to cover the gate structure, a photoresist pattern is formed on the insulating interlayer. Using the photoresist pattern as an etching mask, the insulating interlayer is partially etched using the self-alignment process to form a contact hole that exposes the contact region. Then, a self-aligned contact (SAC) is formed in the contact hole. Because of the self-alignment process, the semiconductor device may have a high degree of integration. However, in some cases, semiconductor devices that are manufactured using the self-alignment process may have poor electrical characteristics.
Semiconductor devices having recessed channel transistors have also been developed. These devices may facilitate providing a proper channel length and may exhibit reduced junction leakage current, particularly in semiconductor devices having unit cell widths of less than about 100 nm. To form these recessed channel transistors, a recess is formed at in upper portion of a substrate by etching the substrate. A gate structure is formed in the recess. An insulating interlayer is then formed on the substrate, and the insulating interlayer is partially etched using an etching mask to form a contact hole that exposes a contact region of the substrate. A pad or a contact that makes contact with the contact region is formed in the contact hole.